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EP9307 Data Sheet
FEATURES
* 200 MHz ARM920T Processor * 16 Kbyte Instruction Cache * 16 Kbyte Data Cache * * * Linux(R), Microsoft(R) Windows(R) CE enabled MMU 100 MHz System Bus
ARM9 SOC with Ethernet, USB, Display and Touchscreen
* * * Touchscreen Interface with ADC 8 x 8 Keypad Scanner One Serial Peripheral Interface (SPI) Port
MaverickCrunchTM Math Engine * Floating point, integer and signal processing instructions * Optimized for digital music compression and decompression algorithms * Hardware interlocks allow in-line coding MaverickKeyTM IDs * 32-bit unique ID can be used for DRM compliance 128-bit random ID Integrated Peripheral Interfaces * 32-bit SDRAM Interface up to 4 banks * 32/16-bit SRAM/FLASH/ROM * Serial EEPROM Interface * 1/10/100 Mbps Ethernet MAC * Three UARTs * Three-port USB 2.0 Full Speed Host (OHCI) (12 Mbits per second) * IrDA Interface * LCD and Raster Interface with Graphics Accelerator
*
*
*
*
* 6-channel or 2-channel Serial Audio Interface (I2S) * 2-channel low-cost Serial Audio Interface (AC'97) Internal Peripherals * 12 Direct Memory Access (DMA) Channels * Real-time Clock with software Trim * Dual PLL controls all clock domains * Watchdog Timer * Two general purpose 16-bit timers * One general purpose 32-bit timer * One 40-bit Debug Timer * Interrupt Controller * Boot ROM Package * 272 pin TFBGA
COMMUNICATIONS PORTS
Serial Audio Interface 12 Channel DMA (3) UARTs w/ IrDA
Peripheral Bus
Clocks & Timers
USER INTERFACE
MaverickCrunchTM ARM920T
Interrupts & GPIO
MaverickKeyTM
D-Cache 16KB
I-Cache 16KB
Bus Bridge
(3) USB Hosts
Boot ROM
MMU
Keypad & Touch Screen I/F Processor Bus
Ethernet MAC
SRAM & Flash I/F
Unified SDRAM I/F
Video/LCD Controller
Graphic Accelerator
MEMORY AND STORAGE
Copyright 2004 Cirrus Logic (All Rights Reserved) AUG `04 DS667PP3 1
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
OVERVIEW
The EP9307 is an ARM920T-based system-on-a-chip (SOC) design with a large peripheral set targeted to a variety of applications: * * * * * * * Thin client computers for business and home Internet radio Internet access devices Industrial computers Specialized terminals Point of sale terminals Test and measurement equipment
and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. A high-performance 1/10/100 Mbps Ethernet Media Access Controller (MAC) is included along with external interfaces to SPI, I2S audio, Raster/LCD, keypad and touchscreen. A three-port USB 2.0 Full Speed Host (OHCI) (12 Mbits per second) and three UARTs are included as well. The EP9307 is a high-performance, low-power RISCbased single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200 MHz (184 MHz for industrial conditions). The ARM core operates from a 1.8 V supply, while the I/O operates at 3.3 V with power usage between 100 mW and 750 mW (dependent on speed).
The EP9307 is one of a series of ARM920T-based devices. The ARM920T microprocessor core with separate 16 Kbyte, 64-way set-associative instruction and data caches is augmented by the MaverickCrunchTM coprocessor enabling high-speed floating point calculations. MaverickKeyTM unique hardware programmed IDs are a solution to the growing concern over secure web content
Table A. Change History
Revision
1 2
Date
July 2004 August 2004 Initial Release. Correct error in pin out table, pages 42 & 43.
Changes
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Table of Contents FEATURES .........................................................................................................1 OVERVIEW .........................................................................................................2
Processor Core - ARM920T ......................................................................................... 6 MaverickCrunchTM Math Engine .................................................................................. 6 MaverickKeyTM Unique ID ............................................................................................ 6 General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) ........................ 6 Ethernet Media Access Controller (MAC) .................................................................... 7 Serial Interfaces (SPI, I2S and AC '97) ........................................................................ 7 Raster/LCD Interface ................................................................................................... 7 Graphics Accelerator ................................................................................................... 8 Touch Screen Interface with 12-bit Analog-to-Digital Converter (ADC) ....................... 8 64-Keypad Interface ..................................................................................................... 8 Universal Asynchronous Receiver/Transmitters (UARTs) ............................................ 9 Internal Boot ROM ....................................................................................................... 9 Triple Port USB Host .................................................................................................... 9 Two-Wire Interface With EEPROM Support ................................................................ 9 Real-Time Clock with Software Trim .......................................................................... 10 PLL and Clocking ....................................................................................................... 10 Timers ........................................................................................................................ 10 Interrupt Controller ..................................................................................................... 10 Dual LED Drivers ....................................................................................................... 10 General Purpose Input/Output (GPIO) ....................................................................... 10 Reset and Power Management ..................................................................................11 Hardware Debug Interface ..........................................................................................11 12-Channel DMA Controller ........................................................................................11
Electrical Specifications .................................................................................12
Absolute Maximum Ratings ....................................................................................... 12 Recommended Operating Conditions ........................................................................ 12 DC Characteristics ..................................................................................................... 13
Timings .............................................................................................................14
Memory Interface ....................................................................................................... 15 Ethernet MAC Interface ............................................................................................ 29 Audio Interface ........................................................................................................... 31 AC'97 ...................................................................................................................... 35 LCD Interface .......................................................................................................... 36 ADC ........................................................................................................................... 37 JTAG .......................................................................................................................... 38
272 Pin TFBGA Package Outline ...................................................................39
272 TFBGA Diagram ................................................................................................. 39 272 Pin TFBGA Pinout (Bottom View) ....................................................................... 40
Acronyms and Abbreviations ........................................................................47 Units of Measurement .....................................................................................47 ORDERING INFORMATION ............................................................................48
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List of Figures
Figure 1. Timing Diagram Drawing Key ................................................................................. 14 Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 15 Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 16 Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 17 Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18 Figure 6. Static Memory Single Word Read Cycle Timing Measurement .............................. 19 Figure 7. Static Memory Single Word Write Cycle Timing Measurement .............................. 20 Figure 8. Static Memory Multiple Word Read 8 Bit Cycle Timing Measurement ................... 21 Figure 9. Static Memory Multiple Word Write 8 bit Cycle Timing Measurement .................... 22 Figure 10. Static Memory Multiple Word Read 16 Bit Cycle Timing Measurement ............... 23 Figure 11. Static Memory Multiple Word Write 16 bit Cycle Timing Measurement ................ 24 Figure 12. Static Memory Burst Read Cycle Timing Measurement ....................................... 25 Figure 13. Static Memory Single Read Wait Cycle Timing Measurement ............................. 26 Figure 14. Static Memory Single Write Wait Cycle Timing Measurement .............................. 27 Figure 15. Static Memory Turnaround Cycle Timing Measurement ....................................... 28 Figure 16. Ethernet MAC Timing Measurement ..................................................................... 30 Figure 17. SPI Single Transfer Timing Measurement ............................................................ 32 Figure 18. Microwire Frame Format, Single Transfer ............................................................ 32 Figure 19. SPI Format with SPH=1 Timing Measurement ..................................................... 33 Figure 20. Inter-IC Sound (I2S) Timing Measurement ........................................................... 34 Figure 21. AC `97 Configuration Timing Measurement .......................................................... 35 Figure 22. LCD Timing Measurement .................................................................................... 36 Figure 23. ADC Transfer Function ......................................................................................... 37 Figure 24. JTAG Timing Measurement .................................................................................. 38 Figure 25. 272 Pin TFBGA Diagram ...................................................................................... 39 Figure 26. 272 Pin TFBGA Pinout .................................................................................... 41
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
List of Tables
Table A. Change History .......................................................................................................... 2 Table B. General Purpose Memory Interface Pin Assignments .............................................. 6 Table C. Ethernet Media Access Controller Pin Assignments ................................................. 7 Table D. Audio Interfaces Pin Assignment .............................................................................. 7 Table E. LCD Interface Pin Assignments ................................................................................ 8 Table F. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8 Table G. 64-Key Keypad Interface Pin Assignments ............................................................... 8 Table H. Universal Asynchronous Receiver / Transmitters Pin Assignments .......................... 9 Table I. Triple Port USB Host Pin Assignments ..................................................................... 9 Table J. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9 Table K. Real-Time Clock with Pin Assignments ................................................................... 10 Table L. PLL and Clocking Pin Assignments ........................................................................ 10 Table M.Interrupt Controller Pin Assignment ........................................................................ 10 Table N. Dual LED Pin Assignments ..................................................................................... 10 Table O. General Purpose Input/Output Pin Assignment ...................................................... 11 Table P. Reset and Power Management Pin Assignments ................................................... 11 Table Q. Hardware Debug Interface ...................................................................................... 11 Table R. 272 Pin Diagram Dimensions .................................................................................. 40 Table S. Pin Descriptions ..................................................................................................... 44 Table T. Pin Multiplex Usage Information ............................................................................. 46
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Processor Core - ARM920T
The ARM920T is a Harvard architecture processor with separate 16 Kbyte instruction and data caches with an 8word line length but a unified memory. The processor utilizes a five-stage pipeline consisting of fetch, decode, execute, memory and write stages. Key features include: * * * * * * * * ARM (32-bit) and Thumb (16-bit compressed) instruction sets 32-bit Advanced Micro-Controller Bus Architecture (AMBA) 16 Kbyte Instruction Cache with lockdown 16 Kbyte Data Cache (programmable write-through or write-back) with lockdown MMU for Linux(R), Microsoft(R) Windows(R) CE and other operating systems Translation Look Aside Buffers with 64 Data and 64 Instruction Entries Programmable Page Sizes of 64 Kbyte, 4 Kbyte, and 1 Kbyte Independent lockdown of TLB Entries
provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP9307 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9307 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today's Internet appliances.
General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH)
The EP9307 features a unified memory address model where all memory devices are accessed over a common address/data bus. A separate internal port is dedicated to the read-only Raster/LCD refresh engine, while the rest of the memory accesses are performed via the Processor bus. The SRAM memory controller supports 8, 16 and 32-bit devices and accommodates an internal boot ROM concurrently with 32-bit SDRAM memory. * * * * * 1-4 banks of 32-bit, 100 MHz SDRAM One internal port dedicated to the Raster/LCD Refresh Engine (Read Only) One internal port dedicated to the rest of the chip via the Processor bus Address and data bus shared between SDRAM, SRAM, ROM, and FLASH memory Both NAND and NOR FLASH memory supported
Table B. General Purpose Memory Interface Pin Assignments
MaverickCrunchTM Math Engine
The MaverickCrunch Engine is a mixed-mode coprocessor designed primarily to accelerate the math processing required to rapidly encode digital audio formats. It accelerates single and double precision integer and floating point operations plus an integer multiply-accumulate (MAC) instruction that is considerably faster than the ARM920T's native MAC instruction. The ARM920T coprocessor interface is utilized thereby sharing its memory interface and instruction stream. Hardware forwarding and interlock allows the ARM to handle looping and addressing while MaverickCrunch handles computation. Features include: * * * * * * * * IEEE-754 single and double precision floating point 32/64-bit integer Add/multiply/compare Integer MAC 32-bit input with 72-bit accumulate Integer Shifts Floating point to/from integer conversion Sixteen 64-bit register files Four 72-bit accumulators
TM
Pin Mnemonic
SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn CSn[7:6] and CSn[3:0] AD[25:0] DA[31:0] DQMn[3:0] WRn RDn WAITn
Pin Description
SDRAM Clock SDRAM Clock Enable SDRAM Chip Selects 3-0 SDRAM RAS SDRAM CAS SDRAM Write Enable Chip Selects 7, 6, 3, 2, 1, 0 Address Bus 25-0 Data Bus 31-0 SDRAM Output Enables / Data Masks SRAM Write Strobe SRAM Read/OE Strobe SRAM Wait Input
MaverickKey
Unique ID
MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC 802.3 topology for a single shared medium with several stations. Multiple MII-compliant PHYs are supported. Features include: * * Supports 1/10/100 Mbps transfer rates for home/small-business/large-business applications Interfaces to an off-chip PHY through industry standard Media Independent Interface (MII)
Table C. Ethernet Media Access Controller Pin Assignments
Table D. Audio Interfaces Pin Assignment
Pin Name
SCLK1 SFRM1
Normal Mode Pin Description
SPI Bit Clock
I2S on SSP Mode Pin Description
I2S Serial Clock
I2S on AC'97 Mode Pin Description
SPI Bit Clock SPI Frame Clock SPI Serial Input SPI Serial Output
SPI Frame Clock I2S Frame Clock I2S Serial Input I2S Serial Output (No I2S Master Clock)
SSPRX1 SPI Serial Input SSPTX1 SPI Serial Output
Pin Mnemonic
MDC MDIO RXCLK MIIRXD[3:0] RXDVAL RXERR TXCLK MIITXD[3:0] TXEN TXERR CRS CLD
Pin Description
Management Data Clock Management Data I/O Receive Clock Receive Data Receive Data Valid Receive Data Error Transmit Clock Transmit Data Transmit Enable Transmit Error Carrier Sense Collision Detect
ARSTn
AC'97 Reset
AC'97 Reset AC'97 Bit Clock AC'97 Frame Clock AC'97 Serial Input AC'97 Serial Output
I2S Master Clock I2S Serial Clock I2S Frame Clock I2S Serial Input I2S Serial Output
ABITCLK AC'97 Bit Clock ASYNC ASDI ASDO AC'97 Frame Clock AC'97 Serial Input AC'97 Serial Output
Raster/LCD Interface
The Raster/LCD interface provides data and interface signals for a variety of display types. It features fully programmable video interface timing for non-interlaced flat panel or dual scan displays. Resolutions up to 1280 x 1024 are supported from a unified SDRAM based frame buffer. A 16-bit PWM provides control for LCD panel contrast. LCD specific features include: * * * * * * * * Timing and interface signals for digital LCD and TFT displays Full programmability for either non-interlaced or dualscan color and grayscale flat panel displays Dedicated data path to SDRAM controller for improved system performance Pixel depths of 4, 8, 16, or 18-bits per pixel or 256 levels of grayscale Hardware Cursor up to 64 x 64 pixels 256 x 18 Color Lookup Table Hardware Blinking 8-bit interface to low end panel
Serial Interfaces (SPI, I2S and AC '97)
The SPI port can be configured as a master or a slave, supporting the National Semiconductor(R), Motorola(R) and Texas Instruments(R) signaling protocols. The AC'97 port supports multiple codecs for multichannel audio output with a single stereo input. The I2S port can be configured to support two channel, 24 bit audio. These ports are multiplexed so that I2S port 0 will take over either the AC'97 pins or the SPI pins. The second and third I2S ports' serial input and serial output pins are multiplexed with EGPIO[4,5,6,13]. The clocks supplied in the first I2S port are also used for the second and third I2S ports. * * * Normal Mode: One SPI Port and one AC'97 Port I2S on SSP Mode: One AC'97 Port and up to three I2S Ports I2S on AC'97 Mode: One SPI Port and up to three I2S Ports
Note: I2S may not be output on AC'97 and SSP ports at the same time.
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Table E. LCD Interface Pin Assignments
Table F. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments
Pin Mnemonic
SPCLK P[17:0] HSYNC/LP VCSYNC/FP BLANK BRIGHT Pixel Clock
Pin Description Pin Mnemonic
Xp, Xm Yp, Ym SXp, SXm SYp, SYm
Pin Description
Touch screen ADC X Axis Touch screen ADC Y Axis Touch screen ADC X Axis Voltage Feedback Touch screen ADC Y Axis Voltage Feedback
Pixel Data Bus [17:0] Horizontal Synchronization/Line Pulse Vertical or Composite Synchronization / Frame Pulse Composite Blank Pulse Width Modulated Brightness
64-Keypad Interface Graphics Accelerator
The EP9307 contains a hardware graphics acceleration engine that improves graphic performance by handling block copy, block fill and hardware line draw operations. The Graphics Accelerator is used in the system to offload graphics operations from the processor. Pixel depths supported by the Graphics Accelerator are 4, 8, 16 or 24 bits per pixel (bpp). The 24 bits per pixel mode can be operated as packed (4 pixels every 3 words) or unpacked (1 pixel per word with the high byte unused.) The block copy operations of the Graphics Accelerator are similar to a DMA (Direct Memory Access) transfer that understands pixel organization, block width, transparency, and transformation from 1bpp to higher 4, 8, 16 or 24 bpp. The line draw operations also allow for solid lines or dashed lines. The colors for line drawing can be either foreground color and background color or foreground color with the background being transparent. The keypad circuitry scans an 8 x 8 array of 64 normally open, single pole switches. Any one or two keys depressed will be de-bounced and decoded. An interrupt is generated whenever a stable set of depressed keys is detected. If the keypad is not utilized, the 16 column/row pins may be used as general purpose I/O. The Keypad interface: * * * * * Provides scanning, debounce and decoding for a 64key array. Scans an 8-row by 8-column matrix. May decode 2 keys at once. Generates an interrupt when a new stable key is determined. Also generates a 3-key reset interrupt.
Table G. 64-Key Keypad Interface Pin Assignments
Pin Mnemonic
COL[7:0] ROW[7:0]
Pin Description
Key Matrix Column Inputs Key Matrix Row Inputs
Alternative Usage
General Purpose I/O General Purpose I/O
Touch Screen Interface with 12-bit Analogto-Digital Converter (ADC)
The touch screen interface performs all sampling, averaging, ADC range checking, and control for a wide variety of analog resistive touch screens. This controller only interrupts the processor when a meaningful change occurs. The touch screen hardware may be disabled and the switch matrix and ADC controlled directly if desired. Features include: * * * Support for 4, 5, 7, or 8-wire analog resistive touch screens. Flexibility - unused lines may be used for temperature sensing or other functions. Touch screen interrupt function.
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Universal Asynchronous Receiver/Transmitters (UARTs)
Three 16550-compatible UARTs are supplied. Two provide asynchronous HDLC (High-level Data Link Control) protocol support for full duplex transmit and receive. The HDLC receiver handles framing, address matching, CRC checking, control-octet transparency, and optionally passes the CRC to the host at the end of the packet. The HDLC transmitter handles framing, CRC generation, and control-octet transparency. The host must assemble the frame in memory before transmission. The HDLC receiver and transmitter use the UART FIFOs to buffer the data streams. A third IrDA(R) compatible UART is also supplied. * UART1 supports modem bit rates up to 115.2 Kbps, supports HDLC and includes a 16 byte FIFO for receive and a 16 byte FIFO for transmit. Interrupts are generated on Rx, Tx and modem status change. UART2 contains an IrDA encoder operating at either the slow (up to 115 Kbps), medium (0.576 or 1.152 Mbps), or fast (4 Mbps) IR data rates. It also has a 16 byte FIFO for receive and a 16 byte FIFO for transmit. UART3 supports HDLC and includes a 16 byte FIFO for receive and a 16 byte FIFO for transmit. Interrupts are generated on Rx and Tx.
Table H. Universal Asynchronous Receiver / Transmitters Pin Assignments
Triple Port USB Host
The USB Open Host Controller Interface (Open HCI) provides full speed serial communications ports at a baud rate of 12 Mbits/sec. Up to 127 USB devices (printer, mouse, camera, keyboard, etc.) and USB hubs can be connected to the USB host in the USB "tieredstart" topology. This includes the following features: Compliance with the USB 2.0 specification Compliance with the Open HCI Rev 1.0 specification Supports both low speed (1.5 Mbps) and full speed (12 Mbps) USB device connections * Root HUB integrated with 3 downstream USB ports * Transceiver buffers integrated, over-current protection on ports * Supports power management * Operates as a master on the bus The Open HCI host controller initializes the master DMA transfer with the AHB bus: * * * * Fetches endpoint descriptors and transfer descriptors Accesses endpoint data from system memory Accesses the HC communication area Writes status and retire transfer descriptor
Table I. Triple Port USB Host Pin Assignments
* * *
*
*
Pin Mnemonic
TXD0 RXD0 CTSn DSRn/DCDn DTRn RTSn EGPIO[0]/RI TXD1/SIROUT RXD1/SIRIN TXD2 RXD2 TENn
Pin Name - Description
UART1 Transmit UART1 Receive UART1 Clear To Send / Transmit Enable UART1 Data Set Ready / Data Carrier Detect UART1 Data Terminal Ready UART1 Ready To Send UART1 Ring Indicator UART2 Transmit / IrDA Output UART2 Receive / IrDA Input UART3 Transmit UART3 Receive HDLC3 Transmit Enable
Pin Mnemonic
USBp[2:0] USBm[2:0]
Pin Name - Description
USB Positive signals USB Negative Signals
Two-Wire Interface With EEPROM Support
The two-wire interface provides communication and control for EEPROM devices.
Table J. Two-Wire Port with EEPROM Support Pin Assignments
Pin Mnemonic
EECLK EEDATA
Pin Name - Description
EEPROM / Two-Wire Interface Clock EEPROM / Two-Wire Interface Data
Alternative Usage
General Purpose I/O General Purpose I/O
Internal Boot ROM
The Internal 16 Kbyte ROM allows booting from FLASH memory, SPI or UART.
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Real-Time Clock with Software Trim
The software trim feature on the real time clock (RTC) provides software controlled digital compensation of the 32.768 KHz crystal oscillator. This compensation is accurate to 1.24 sec/month.
Table K. Real-Time Clock with Pin Assignments
sensitive, active low level sensitive, rising edge triggered, falling edge triggered, or combined rising/falling edge triggered. * * Supports 64 interrupts from a variety of sources (such as UARTs, GPIO, and key matrix) Routes interrupt sources to either the ARM920T's IRQ or FIQ (Fast IRQ) inputs Three dedicated off-chip interrupt lines operate as active high level sensitive interrupts Any of the 16 GPIO lines maybe configured to generate interrupts Software supported priority mask for all FIQs and IRQs
Table M. Interrupt Controller Pin Assignment
Pin Mnemonic
RTCXTALI RTCXTALO
Pin Name - Description
Real-Time Clock Oscillator Input Real-Time Clock Oscillator Output
* * *
PLL and Clocking
The Processor and the Peripheral Clocks operate from a single 14.7456 MHz crystal. The Real Time Clock operates from a 32.768 KHz crystal oscillator.
Table L. PLL and Clocking Pin Assignments
Pin Mnemonic
INT[2:0]
Pin Name - Description
External Interrupts 2, 1, 0
Dual LED Drivers
Two pins are assigned specifically to drive external LEDs.
Table N. Dual LED Pin Assignments
Pin Mnemonic
XTALI XTALO VDD_PLL GND_PLL
Pin Name - Description
Main Oscillator Input Main Oscillator Output Main Oscillator Power Main Oscillator Ground
Pin Mnemonic
GRLED REDLED
Pin Name Description
Green LED Red LED
Alternative Usage
General Purpose I/O General Purpose I/O
Timers
The Watchdog Timer insures proper operation by requiring periodic attention to prevent a reset-on-timeout. Two 16-bit timers operate as free running down-counters or as periodic timers for fixed interval interrupts and have a range of 0.03 ms to 4.27 seconds. One 32-bit timer, plus a 6-bit prescale counter, has a range of 0.03 s to 73.3 hours. One 40-bit debug timer, plus a 6-bit prescale counter, has a range of 1.0 s to 12.7 days.
General Purpose Input/Output (GPIO)
The 14 EGPIO pins may each be configured individually as an output, an input, or an interrupt input. There are 22 pins that may alternatively be used as input, output, or open-drain pins, but do not support interrupts. These pins are: * Key Matrix ROW[7:0], COL[7:0] * Ethernet MDIO * Both LED Outputs * EEPROM Clock and Data * GGPIO[2] * HGPIO[7:2] 6 pins may alternatively be used as inputs only: * CTSn, DSRn/DCDn * 4 Interrupt Lines 2 pins may alternatively be used as outputs only: * RTSn * ARSTn
Interrupt Controller
The interrupt controller allows up to 62 interrupts to generate an Interrupt Request (IRQ) or Fast Interrupt Request (FIQ) signal to the processor core. Thirty-two hardware priority assignments are provided for assisting IRQ vectoring, and two levels are provided for FIQ vectoring. This allows time critical interrupts to be processed in the shortest time possible. Internal interrupts may be programmed as active high or active low level sensitive inputs. GPIO pins programmed as interrupts may be programmed as active high level
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Table O. General Purpose Input/Output Pin Assignment
decrement, or stay at the same value. All DMA addresses are physical, not virtual addresses.
Pin Mnemonic
EGPIO[15] EGPIO[13:0] FGPIO[7] FGPIO[5] FGPIO[0]
Pin Name - Description
Expanded General Purpose Input / Output Pins with Interrupts Expanded General Purpose Input / Output Pins with Interrupts
Reset and Power Management
The chip may be reset through the PRSTn pin or through the open drain common reset pin, RSTOn. Clocks are managed on a peripheral-by-peripheral basis and may be turned off to conserve power. The processor clock is dynamically adjustable from 0 to 200 MHz (184 MHz for industrial conditions).
Table P. Reset and Power Management Pin Assignments
Pin Mnemonic
PRSTn RSTOn
Pin Name - Description
Power On Reset User Reset In/Out - Open Drain - Preserves Real Time Clock value
Hardware Debug Interface
The JTAG interface allows use of ARM's Multi-ICE or other in-circuit emulators.
Table Q. Hardware Debug Interface
Pin Mnemonic
TCK TDI TDO TMS TRSTn
Pin Name - Description
JTAG Clock JTAG Data In JTAG Data Out JTAG Test Mode Select JTAG Port Reset
12-Channel DMA Controller
The DMA module contains 12 separate DMA channels. These may be used for peripheral-to-memory or memory-to-peripheral access. Two of these are dedicated to memory-to-memory transfers. Each DMA channel is connected to the 16-bit DMA request bus. The request bus is a collection of requests, Serial Audio and UARTs. Each DMA channel can be used independently or dedicated to any request signal. For each DMA channel, source and destination addressing can be independently programmed to increment,
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Electrical Specifications
Absolute Maximum Ratings
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter Symbol
RVDD CVDD VDD_PLL VDD_ADC (Note 1)
Min
-
Max
3.96 2.16 2.16 3.96 2 10 50 RVDD+0.3 +125
Unit
V V V V W mA mA V C
Power Supplies
Total Power Dissipation Input Current per Pin, DC (Except supply pins) Output current per pin, DC Digital Input voltage Storage temperature
(Note 2)
-0.3 -40
Note:
1. Includes all power generated due to AC and/or DC output loading. 2. The power supply pins are at maximum values listed in "Recommended Operating Conditions", below. 3. At ambient temperatures above 70 C, total power dissipation must be limited to less than 2.5 Watts.
WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Recommended Operating Conditions
(All grounds = 0 V, all voltages with respect to 0 V)
Parameter Symbol
RVDD CVDD VDD_PLL VDD_ADC TA TA FCLK FCLK HCLK HCLK
Min
3.0 1.65 1.65 3.0 0 -40 -
Typ
3.3 1.80 1.80 3.3 +25 +25 -
Max
3.6 1.94 1.94 3.6 +70 +85 200 184 100 92
Unit
V V V V C C MHz MHz MHz MHz
Power Supplies
Operating Ambient Temperature - Commercial Operating Ambient Temperature - Industrial Processor Clock Speed - Commercial Processor Clock Speed - Industrial System Clock Speed - Commercial System Clock Speed - Industrial
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
DC Characteristics
(TA = 0 to 70 C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V; All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)
Parameter
High level output voltage Low level output voltage High level input voltage Low level input voltage High level leakage current Low level leakage current Vin = 3.3 V Vin = 0 Iout = -4 mA Iout = 4 mA (Note 5) (Note 5) (Note 5) (Note 5) (Note 4)
Symbol
Voh Vol Vih Vil Iih Iil
Min
0.85 x RVDD 0.65 x RVDD -0.3 -
Max
0.15 x RVDD VDD + 0.3 0.35 x RVDD 10 -10
Unit
V V V V A A
Parameter
Power Supply Pins (Outputs Unloaded)
Power Supply Current: Low-Power Mode Supply Current CVDD/VDD_PLL Total RVDD CVDD/VDD_PLL Total RVDD
Min
Typ
Max
Unit
-
200 20 2.5 1.0
-
mA mA mA mA
Note:
4. For open drain pins, high level output voltage is dependent on the external load. 5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table S on page 44). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not driven and programmed as an input, it should be tied to power or ground through its own resistor.
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
Clock High to Low High/Low to High Bus Change Bus Valid Undefined/Invalid Valid Bus to High Impedance State Bus/Signal Omission
Figure 1. Timing Diagram Drawing Key
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. * TA = 0 to 70 C * CVDD = VDD_PLL = 1.8V * RVDD = 3.3 V * All grounds = 0 V * Logic 0 = 0 V, Logic 1 = 3.3 V * Output loading = 50 pF * Timing reference levels = 1.5 V * The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between 33 MHz and 100 MHz (92 MHz for industrial conditions).
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Copyright 2004 Cirrus Logic (All Rights Reserved)
DS667PP3
EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Memory Interface
Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes.
Parameter
SDCLK high time SDCLK low time SDCLK rise/fall time Signal delay from SDCLK rising edge time Signal hold from SDCLK rising edge time DQMn delay from SDCLK rising edge time DQMn hold from SDCLK rising edge time DA valid setup to SDCLK rising edge time DA valid hold from SDCLK rising edge time
Symbol
tclk_high tclk_low tclkrf td th tDQd tDQh tDAs tDAh
Min
-
Typ
(tHCLK)/2 (tHCLK)/2 3 8 4 6 6 2 2
Max
-
Unit
ns ns ns ns ns ns ns ns ns
SDRAM Load Mode Register Cycle
tclk_low tclk_high
tclkrf SDCLK
td SDCSn
th
RASn
CASn
SDWEn
DQMn
AD
OP-Code
DA
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
SDRAM Burst Read Cycle
tclk_low SDCLK
tclk_high
tclkrf td SDCSn th
RASn
CASn
SDWEn tDQd DQMn tDQh
AD td tDAs DA tDAh
Figure 3. SDRAM Burst Read Cycle Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
SDRAM Burst Write Cycle
tclk_low SDCLK td SDCSn th
tclk_high
tclkrf
th
RASn
CASn
SDWEn
DQMn
AD
DA
Figure 4. SDRAM Burst Write Cycle Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
SDRAM Auto Refresh Cycle
tclk_low SDCLK
tclk_high
tclkrf td SDCSn 7 b d e th
RASn
CASn
SDWEn
Note: Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory Single Word Read Cycle
Parameter
AD setup to RDn assert time AD hold from RDn deassert time RDn assert time CSn assert to RDn assert delay time CSn deassert to RDn deassert delay time CSn assert to DQMn assert delay time CSn deassert to DQMn deassert delay time DA setup to RDn deassert time DA hold from RDn deassert time
Symbol
tADs tADh tRDpw tRDd tRDh tDQMd tDQMh tDAs tDAh
Min
0
Typ
5 tHCLK x 2 tHCLK x (WST1 + 2) 0 0 0 0 tHCLK + 6 0
Max
tHCLK x 33 -
Unit
ns ns ns ns ns ns ns ns ns
See "Timing Conditions" on page 14 for definition of HCLK.
t ADs AD
t AD h
CSn
W Rn t R Dd1 RDn t D QMd1 t R D pw t D QMd2 h t R Dd2 h
DQMn
t DAs DA
t DAh
W AIT
Figure 6. Static Memory Single Word Read Cycle Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory Single Word Write Cycle
Parameter
AD setup to WRn assert time AD hold from WRn deassert time WRn deassert to CSn deassert time CSn to WRn assert delay time WRn assert time CSn to DQMn assert delay time WRn deassert to DQMn deassert time WRn deassert to DA transition time
Symbol
tADs tADh tCSh tWRd tWRpw tDQMd tDQMh tDAh
Min
-
Typ
tHCLK tHCLK x 3 tHCLK 0 tHCLK x (WST1 + 1) 0 0 tHCLK
Max
-
Unit
ns ns ns ns ns ns ns ns
tADs AD tCSh tWRd WRn tWRpw
tADh
CSn
RDn DQMn tDQMd tDQMh
tDAh DA
WAIT
Figure 7. Static Memory Single Word Write Cycle Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory 32-bit Read on 8-bit External Bus
Parameter
AD setup to RDn assert time RDn assert to Address 1 transition time Address 2 assert time Address 3 assert time AD transition to RDn deassert time AD hold from RDn deassert time RDn assert time CSn assert to RDn assert delay time CSn deassert to RDn deassert delay time CSn assert to DQMn assert delay time CSn deassert to DQMn deassert delay time DA setup to AD transition time DA to RDn setup time AD transition to DA transition hold time RDn deassert to DA transition hold time
Symbol
tADs tAD1 tAD2 tAD3 tAD4 tADh tRDpwL tRDd tRDh tDQMd tDQMh tDAs1 tDAs2 tDAh1 tDAh2
Min
-
Typ
tHCLK tHCLK x (WST1 + 1) tHCLK x (WST1 + 1) tHCLK x (WST1 + 1) tHCLK x (WST1 + 2) tHCLK x 2 tHCLK x (4 x WST1 + 5) 0 0 0 0 6 tHCLK + 6 0 0
Max
-
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t AD s AD
t AD 1
t AD2
t AD 3
t AD 4
t ADh
CSn
W Rn tR D d RDn t D QMd DQMn t DAh1 DA t DAs1 W AIT t D As 1 t DAs1 t DAs2 t D Ah1 t RD PwL t R Dh
t D QMh t DAh1
1
t D Ah2
Figure 8. Static Memory Multiple Word Read 8 Bit Cycle Timing Measurement
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory 32-bit Write on 8-bit External Bus
Parameter
AD setup to WRn assert time WRn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time WRn deassert time CSn to DQMn assert delay time DQMn assert time DQMn deassert time WRn/DQMn deassert to DA transition time
Symbol
tADs tADd tADh tCSh tWRd tWRpwL tWRpwH tDQMd tDQMpwL tDQMpwH tDAh
Min
-
Typ
tHCLK tHCLK tHCLK x 3 tHCLK 0 tHCLK x (WST1 + 1) tHCLK x 2 0 tHCLK x (WST1 + 1) tHCLK x 2 tHCLK
Max
-
Unit
ns ns ns ns ns ns ns ns ns ns ns
t AD s AD
t AD d
t AD d
t A Dd
t AD h
CSn tW R d W Rn t W R pwH RDn t D QM d DQMn t D Q M pwH t D QM pw H t DQ M pwH t D Q M pwL t D QM pw L t D Q M pwL t W R pwH t W R pwH t W R pwL t W R pwL t W R pwL t C Sh
DA t D Ah W AIT
Figure 9. Static Memory Multiple Word Write 8 bit Cycle Timing Measurement
t D Ah
t DAh
t D Ah
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory 32-bit Read on 16-bit External Bus
Parameter
AD setup to RDn assert time RDn assert to AD transition time AD transition to RDn deassert time AD hold from RDn deassert time RDn assert time CSn to RDn assert delay time CSn to RDn deassert delay time CSn to DQMn assert delay time CSn to DQMn deassert delay time DA to ADsetup time DA to RDn setup time AD transition to DA transition hold time RDn deassert to DA transition hold time
Symbol
tADs tADd1 tADd2 tADh tRDpwL tRDd tRDh tDQMd tDQMh tDAs1 tDAs2 tDAh1 tDAh2
Min
-
Typ
tHCLK tHCLK x (WST1 + 1) tHCLK x (WST1 + 2) tHCLK x 2 tHCLK x (2 x WST1 + 3) 0 0 0 0 6 tHCLK + 6 0 0
Max
-
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns
tADs AD
tADd1
tADd2
tADh
CSn
WRn RDn
tRDd tRDpwl tDQMd tDQMh
tRDh
DQMn
tDAs1 DA
tDAh1
tDAs2
tDAh2
WAIT
Figure 10. Static Memory Multiple Word Read 16 Bit Cycle Timing Measurement
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory 32-bit Write on 16-bit External Bus
Parameter
AD setup to WRn assert time WRn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time WRn deassert time CSn to DQMn assert delay time DQMn assert time DQMn deassert time WRn/DQMn deassert to DA transition time WRn/DQMn deassert to DA transition time
Symbol
tADs tADd tADh tCSh tWRd tWRpwL tWRpwH tDQMd tDQMpwL tDQMpwH tDAh1 tDAh2
Min
-
Typ
tHCLK tHCLK 2 x tHCLK tHCLK 0 tHCLK x (WST1 + 1) tHCLK x 2 0 tHCLK x (WST1 + 1) tHCLK x 2 tHCLK tHCLK
Max
-
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
tADs AD
tADd
tADh
CSn tWRd WRn tWRpwL tWRpwH tWRpwL tCSh
RDn tDQMd DQMn tDQpwL tDQpwH tDAh1 DA tDAh2 tDQpwL
WAIT
Figure 11. Static Memory Multiple Word Write 16 bit Cycle Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory Burst Read Cycle
Parameter
CSn assert to Address 1 transition time Address 2 assert time AD hold from CSn deassert time CSn assert time CSn to RDn assert delay time RDn assert time CSn to DQMn assert delay time DQMn assert time DA to AD setup time DA to CSn setup time AD transition to DA transition hold time CSn deassert to DA transition hold time
Symbol
tADd1 tADd2 tADh tCSpw tRDd tRDpw tDQMd tDQMpw tDAs1 tDAs2 tDAh1 tDAh2
Min
0
Typ
tHCLK x (WST1 + 1) tHCLK x (WST2 + 1) tHCLK x 2 tHCLK x ((WST1 + 1) + 4(WST2 + 1)) 0 tHCLK x ((WST1 + 1) + 4(WST2 + 1)) 4 tHCLK x ((WST1 + 1) + 4(WST2 + 1)) 6 tHCLK + 6 0 0
Max
-
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
Note:
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
tADd1 AD
tADd2
tADd2
tADh
CSn
tCSpw
WRn tRDd RDn tDQMd tRDpw
DQMn
tDQMpw tDAh1 tDAh1 tDAh1 tDAh2
DA tDAs1 WAIT tDAs1 tDAs1 tDAs2
Figure 12. Static Memory Burst Read Cycle Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory Single Read Wait Cycle
Parameter
CSn assert to WAIT time WAIT assert time WAIT to CSn deassert delay time
Symbol
tWAITd tWAITpw tCSnd
Min
tHCLK x 2 tHCLK x 3
Typ
-
Max
tHCLK x (WST1 - 2) tHCLK x 510 tHCLK x 5
Unit
ns ns ns
AD
CSn
WRn
RDn DQMn
DA
WAIT
tWAITd
tWAITpw
tCSnd
Figure 13. Static Memory Single Read Wait Cycle Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory Single Write Wait Cycle
Parameter
WAIT to WRn deassert delay time CSn assert to WAIT time WAIT assert time WAIT to CSn deassert delay time
Symbol
tWRd tWAITd tWAITpw tCSnd
Min
tHCLK x 2 tHCLK x 2 tHCLK x 3
Typ
-
Max
tHCLK x 4 tHCLK x (WST1 - 2) tHCLK x 510 tHCLK x 5
Unit
ns ns ns ns
AD
CSn tW Rd WRn
RDn DQMn
DA tW AITd WAIT tCSnd
tW AITpw
Figure 14. Static Memory Single Write Wait Cycle Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Static Memory Turnaround Cycle
Parameter
CSnX deassert to CSnY assert time
Symbol
tBTcyc
Min
-
Typ
tHCLK x (IDCY+1)
Max
-
Unit
ns
Note:
X and Y represent any two chip select numbers.
tBTcyc AD
X CSn0
Y CSn1
WRn
RDn
DQMn
DA
WAIT
Figure 15. Static Memory Turnaround Cycle Timing Measurement
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Ethernet MAC Interface
Min Parameter Symbol 10 Mbit mode
140 140 0 140 140 10 10 400 160 160 10 10 -
Typ 10 Mbit mode
400 200 200 10 400 200 200 15 15 -
Max 10 Mbit mode
260 260 25 5 260 260 5 5 300
100 Mbit mode
14 14 0 14 14 10 10 400 160 160 10 10 -
100 Mbit mode
40 20 20 10 40 20 20 15 15 -
100 Mbit mode
26 26 25 5 26 26 5 5 300
Unit
TXCLK cycle time TXCLK high time TXCLK low time TXCLK to signal transition delay time TXCLK rise/fall time RXCLK cycle time RXCLK high time RXCLK low time RXDVAL/RXERR setup time RXDVAL/RXERR hold time RXCLK rise/fall time MDC cycle time MDC high time MDC low time MDC rise/fall time MDIO setup time (STA sourced) MDIO hold time (STA sourced) MDC to MDIO signal transition delay time (PHY sourced)
tTX_per tTX_high tTX_low tTXd tTXrf tRX_per tRX_high tRX_low tRXs tRXh tRXrf tMDC_per tMDC_high tMDC_low tMDCrf tMDIOs tMDIOh tMDIOd
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium. PHY - Ethernet physical layer interface.
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
tTX_high TXCLK MII_TXD[3:0]/ TXEN/ TXERR tTXd tTX_per
tTX_low
tTXrf
tRXrf RXCLK MII_RXD[3:0]/ RXDVAL/ RXERR tRXh tRXs
tRX_low
tRX_high
tRX_per
tMDCrf MDC MDIO (Sourced by STA) tMDC_high tMDC_low tMDIOs tMDIOh
tMDC_per
MDC MDIO (Sourced by PHY)
tMDIOd
Figure 16. Ethernet MAC Timing Measurement
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Audio Interface
The following table contains the values for the timings of each of the SPI modes.
Parameter
SCLK cycle time SCLK high time SCLK low time SCLK rise/fall time Data from master valid delay time Data from master setup time Data from master hold time Data from slave valid delay time Data from slave setup time Data from slave hold time
Symbol
tclk_per tclk_high tclk_low tclkrf tDMd tDMs tDMh tDSd tDSs tDSh
Min
-
Typ
tspix_clk (tspix_clk)/2 (tspix_clk)/2 4.5 / 1.5 2 20 40 2 20 40
Max
-
Unit
ns ns ns ns ns ns ns ns ns ns
Note:
tspix_clk is programmable by the user.
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Texas Instruments' Synchronous Serial Format
tclk_per tclk_high SCLK tclk_low SFRM SSPTXD/ SSPRXD tclkrf
MSB 4 to 16 bits
LSB
Figure 17. SPI Single Transfer Timing Measurement
Microwire
tclk_high
tclk_per
tclkrf
SCLK
tclk_low
SFRM
SSPTXD
MSB
LSB
8-bit control SSPRXD
0 MSB LSB
4 to 16 bits output data
Figure 18. Microwire Frame Format, Single Transfer
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Motorola SPI
tclk_per tclk_high SCLK (SPO=0) tclk_low SCLK (SPO=1) tDMs SSPTXD from master tDMd tDSd SSPRXD from slave SFRM tDSs MSB t DSd LSB MSB t DMh LSB tclkrf
Figure 19. SPI Format with SPH=1 Timing Measurement
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Inter-IC Sound - I2S
Parameter
SCLK cycle time SCLK high time SCLK low time SCLK rise/fall time SCLK to LRCLK assert delay time LRCLK from SCLK assert hold time SDI to SCLK deassert setup time SDI from SCLK deassert hold time SCLK to SDO assert delay time SDO from SCLK assert hold time Note: ti2s_clk is programmable by the user.
Symbol
tclk_per tclk_high tclk_low tclkrf tLRs tLRh tSDIs tSDIh tSDOd tSDOh
Min
-
Typ
ti2s_clk (ti2s_clk) / 2 (ti2s_clk) / 2 4 1.5 1.5 20 10 4 4
Max
-
Unit
ns ns ns ns ns ns ns ns ns ns
tclk_per tclk_high
SCLK
tclk_low
tclkrf
tLRs
LRCLK
tLRh
tSDOs
SDO/SDI
tSDOh tSDIs tSDIh
Figure 20. Inter-IC Sound (I2S) Timing Measurement
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
AC'97
Parameter
ABITCLK input cycle time ABITCLK input high time ABITCLK input low time ABITCLK input rise time ABITCLK input fall time ASDI setup to ABITCLK falling ASDI hold after ABITCLK falling ASDI input rise/fall time ABITCLK rising to ASDO/ASYNC valid, CL = 55 pF ASYNC/ASDO rise time, CL = 55 pF ASYNC/ASDO fall time, CL = 55 pF
Symbol
tclk_per tclk_high tclk_low tclkr tclkf ts th trfin tco trout tfout
Min
36 36 2 2 10 10 2 2 2 2
Typ
81.4 23 53 -
Max
45 45 6 6 6 15 6 6
Unit
ns ns ns ns ns ns ns ns ns ns ns
tclk_per ABITCLK tclkrf r
tclk_high tclk_low
tclkrf f
th ts
trfin
ASDI
ASDO
tfoutt fout /t
rfout
tco tco
tco ASYNC
trout
rfout
ttfout rfout
Figure 21. AC `97 Configuration Timing Measurement
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
LCD Interface
Parameter
SPCLK rising time SPCLK falling time SPCLK rising edge to control signal transition time SPCLK rising edge to data transition time SPCLK falling edge to control signal transition time SPCLK falling edge to data transition time Data valid time
Symbol
tclkr tclkf tCD tDD tCDi tDDi tDv
Min
-
Typ
5 5 1 0 (tSPCLK)/2 (tSPCLK)/2 tSPCLK
Max
-
Unit
ns ns ns ns ns ns ns
tclkr
SPCLK HSYNC/ V_CSYNC/ BLANK/ BRIGHT P [17:0]
tclkf
tCD tDD tDv
tclkr
SPLCK HSYNC/ V_CSYNC/ BLANK/ BRIGHT P [17:0]
tclkf
tCDi
tDDi tDv
Figure 22. LCD Timing Measurement
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
ADC
Parameter
Resolution Integral non-linearity Offset error Full scale error Maximum sample rate Channel switch settling time Noise (RMS) - typical Note: ADIV = 0 ADIV = 1 ADIV = 0 ADIV = 1
Comment
No missing codes Range of 0 to 3.3 V
Value
50K counts (approximate) 0.01% 15 0.2% 3750 925 500 2 120
Units
mV
Samples per second Samples per second s ms V
ADIV refers to bit 16 in the KeyTchClkDiv register. ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4. ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16.
61A8
0000 FFFF
9E58 0 Vref/2 Vref
A/D Converter Transfer Function (approximately 25,000 counts)
Figure 23. ADC Transfer Function
Using the ADC: This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay between each successful conversion and the issue of the next conversion command, or else the returned value of successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion. Note that reading TSXYResult during a conversion will not affect the result of the ongoing process. The following is a recommended procedure for safely polling the ADC from software: 1. Read the TSXYResult register into a local variable to initiate a conversion. 2. If the value of bit 31 of the local variable is '0', repeat step 1. 3. Delay long enough to meet the maximum sample rate as shown above. 4. Mask the local variable with 0xFFFF to remove extraneous data. 5. If signed mode is used, do a sign extend of the lower halfword. 6. Return the sampled value.
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Copyright 2004 Cirrus Logic (All Rights Reserved)
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
JTAG
Parameter
TCK clock period TCK clock high time TCK clock low time TMS/TDI to clock rising setup time Clock rising to TMS/TDI hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance
Symbol
tclk_per tclk_high tclk_low tJPs tJPh tJPco tJPzx tJPxz
Min
100 50 50 20 45 -
Max
30 30 30
Units
ns ns ns ns ns ns ns ns
TMS
TDI tclk_per tclk_high TCK tJPzx TDO tJPco tJPxz tclk_low tJPs tJPh
Figure 24. JTAG Timing Measurement
(c)
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Copyright 2004 Cirrus Logic (All Rights Reserved)
DS667PP3
EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
272 Pin TFBGA Package Outline
272 TFBGA Diagram
Figure 25. 272 Pin TFBGA Diagram
D
0.600 REF
E1 e
e
ddd Ob
A A2 c A1
ddd
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DS667PP3
Copyright 2004 Cirrus Logic (All Rights Reserved)
D1
E
39
EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Table R. 272 Pin Diagram Dimensions
dimension in mm Symbol MIN
A A1 A2 b c D D3 E E3 e ddd 1.35 0.23 0.65 0.35 0.21 13.95 12.75 13.95 12.75 0.75
dimension in inches MAX
1.45 0.33 0.75 0.45 0.31 14.05 12.85 14.05 12.85 0.85 0.10
NOM
1.40 0.28 0.70 0.40 0.26 14.00 12.80 14.00 12.80 0.80
MIN
0.053 0.009 0.026 0.014 0.0083 0.549 0.502 0.549 0.502 0.030
NOM
0.055 0.011 0.028 0.016 0.0102 0.551 0.504 0.551 0.504 0.031
MAX
0.057 0.013 0.030 0.018 0.0122 0.553 0.506 0.553 0.506 0.033 0.004
Note:
1. Controlling Dimension: Millimeter. 2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls. 3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C. 4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. 5. Reference Document: JEDEC MO-151, BAL-2
272 Pin TFBGA Pinout (Bottom View)
The following table shows the 272 pin TFBGA pinout. (For better understanding, compare the coordinates on the x and y axis on Figure 26, "272 Pin TFBGA Pinout", on page 41 with Figure 25, "272 Pin TFBGA Diagram", on page 39. * VDD_core is vddc. * VDD_ring is vddr. * GND_core is gndc. * GND_ring is gndr.
(c)
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Copyright 2004 Cirrus Logic (All Rights Reserved)
DS667PP3
Figure 26. 272 Pin TFBGA Pinout
(c)
DS667PP3 Copyright 2004 Cirrus Logic (All Rights Reserved) 41
1 U T R
NC NC P[9]
2
NC NC HSYNC P[10] P[16] AD[0] AD[2] DA[12] DA[14] DA[20] CASn
3
P[8] V_CSYNC P[6] P[11] P[15]
4
P[4] P[7] P[5] P[3] P[13]
5
P[1] P[2] P[0] AD[15] P[12] P[17] BLANK vddr vddr vddr vddr AD[5] DA[15]
6
DA[6] DA[7] AD[14] AD[13] DA[5] gndr gndr gndr vddc vddc gndr gndr AD[21]
7
DA[3] AD[11] DA[4] AD[12] vddr gndr
8
AD[10] AD[9] DA[1] DA[2] vddr vddc
9
DA[0] DSRn DTRn AD[8] vddr vddc
10
TDO TMS TDI TCK vddr gndr
11
NC gndr BOOT[0] BOOT[1] EECLK gndr
12
SCLK[1] SFRM[1] ASYNC EEDAT ASDO ROW[6] gndr
13
SSPRX[1] INT[2]
14
INT[1] INT[0]
15
RTSn USBp[1] USBm[0] GGPIO[2] TXD[0] ROW[0] PLL_GND COL[2] COL[6] PRSTn
16
USBm[1] NC ABITCLK RXD[1] TXD[1] ROW[3] XTALI COL[1] CSn[0] COL[7]
17
NC NC USBp[0] RXD[2] TXD[2] ROW[2] XTALO COL[0] COL[3] RSTOn
U T R P N M L K J H G F E D C B A
EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
SSPTX[1] PWMOUT GRLED CTSn ROW[4] ROW[7] COL[4] vddr vddr RDLED RXD[0] ROW[1] ROW[5] PLL_VDD COL[5] EGPIO[8]
P SPCLK N
P[14]
M BRIGHT L K J
DA[9] AD[4] AD[6]
DQMn[1] DQMn[2] AD[1] DA[10] AD[7] DA[19] DA[21] DA[8] DA[11] DA[13] DA[16] AD[22]
gndc gndc gndc
gndc
gndc gndc
vddc vddc gndr gndr
H DA[18] G DQMn[0] F
RASn
gndc
gndc
EGPIO[9] EGPIO[10] EGPIO[11] RTCXTALO RTCXTALI sYm sXp Ym Xp ARSTn USBm[2] sYp sXm Yp Xm ADC_VDD ASDI
SDCSn[1] SDCSn[0] DQMn[3] DA[22] SDCLK CSn[3] CSn[6] AD[3]
gndr DA[17] DA[28] HGPIO[5] HGPIO[3] HGPIO[2]
gndr vddr HGPIO[4] WRn AD[17] RDn
vddc vddr AD[16] MDIO RXCLK
vddc vddr MDC MIIRXD[2]
gndr MIIRXD[0] RXERR TXCLK
EGPIO[7] EGPIO[5] ADC_GND EGPIO[6] TXERR EGPIO[2] EGPIO[4] EGPIO[3] EGPIO[0] TRSTn USBp[2] WAITn
E SDCSn[2] SDWEN D SDCSn[3] C AD[23] B AD[25] A CSn[1] 1
DA[23] DA[26] CSn[2] CSn[7]
DA[24] HGPIO[7] HGPIO[6] DA[25] AD[20] AD[24] DA[30] DA[29] AD[19] AD[18] DA[27]
MIITXD[3] EGPIO[12] EGPIO[1] MIITXD[0] TXEN CRS CLD EGPIO[13]
MIIRXD[1] MIITXD[2]
FGPIO[5] EGPIO[15] FGPIO[7] FGPIO[0]
SDCLKEN DA[31]
MIIRXD[3] RXDVAL MIITXD[1]
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Pin List
The following Thin-profile Fine-pitch Ball Grid Array (TFBGA) ball assignment table is sorted in order of ball.
Ball
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8
Signal
CSn[1] CSn[7] SDCLKEN DA[31] DA[29] DA[27] HGPIO[2] RDn MIIRXD[3] RXDVAL MIITXD[1] CRS FGPIO[7] FGPIO[0] WAITn USBm[2] ASDI AD[25] CSn[2] CSn[6] AD[20] DA[30] AD[18] HGPIO[3] AD[17] RXCLK MIIRXD[1] MIITXD[2] TXEN FGPIO[5] EGPIO[15] USBp[2] ARSTn ADC_VDD AD[23] DA[26] CSn[3] DA[25] AD[24] AD[19] HGPIO[5] WRn
Ball
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 G1 G2 G3 G4 G5 G6 G12 G13
Signal
SDCSn[2] SDWEN DA[22] AD[3] DA[15] AD[21] DA[17] vddr vddr vddr MIIRXD[0] TXERR EGPIO[2] EGPIO[4] EGPIO[3] sXp sXm RASn SDCSn[1] SDCSn[0] DQMn[3] AD[5] gndr gndr gndr vddc vddc gndr EGPIO[7] EGPIO[5] ADC_GND EGPIO[6] sYm sYp DQMn[0] CASn DA[21] AD[22] vddr gndr gndr EGPIO[9]
Ball
J10 J12 J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K6 K8 K9 K10 K12 K13 K14 K15 K16 K17 L1 L2 L3 L4 L5 L6 L12 L13 L14 L15 L16 L17 M1 M2 M3 M4 M5 M6 M7 M8
Signal
gndc vddc vddr COL[5] COL[6] CSn[0] COL[3] AD[4] DA[12] DA[10] DA[11] vddr gndr gndc gndc gndc vddc COL[4] PLL_VDD COL[2] COL[1] COL[0] DA[9] AD[2] AD[1] DA[8] BLANK gndr gndr ROW[7] ROW[5] PLL_GND XTALI XTALO BRIGHT AD[0] DQMn[1] DQMn[2] P[17] gndr gndr vddc
Ball
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8
Signal
SPCLK P[10] P[11] P[3] AD[15] AD[13] AD[12] DA[2] AD[8] TCK BOOT[1] EEDAT GRLED RDLED GGPIO[2] RXD[1] RXD[2] P[9] HSYNC P[6] P[5] P[0] AD[14] DA[4] DA[1] DTRn TDI BOOT[0] ASYNC SSPTX[1] PWMOUT USBm[0] ABITCLK USBp[0] NC NC V_CSYNC P[7] P[2] DA[7] AD[11] AD[9]
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DS667PP3
EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Ball
C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
Signal
MDIO MIIRXD[2] TXCLK MIITXD[0] CLD EGPIO[13] TRSTn Xp Xm SDCSn[3] DA[23] SDCLK DA[24] HGPIO[7] HGPIO[6] DA[28] HGPIO[4] AD[16] MDC RXERR MIITXD[3] EGPIO[12] EGPIO[1] EGPIO[0] Ym Yp
Ball
G14 G15 G16 G17 H1 H2 H3 H4 H5 H6 H8 H9 H10 H12 H13 H14 H15 H16 H17 J1 J2 J3 J4 J5 J6 J8
Signal
EGPIO[10] EGPIO[11] RTCXTALO RTCXTALI DA[18] DA[20] DA[19] DA[16] vddr vddc gndc gndc gndc gndr vddr EGPIO[8] PRSTn COL[7] RSTOn AD[6] DA[14] AD[7] DA[13] vddr vddc gndc
Ball
M9 M10 M11 M12 M13 M14 M15 M16 M17 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17
Signal
vddc gndr gndr ROW[6] ROW[4] ROW[1] ROW[0] ROW[3] ROW[2] P[14] P[16] P[15] P[13] P[12] DA[5] vddr vddr vddr vddr EECLK ASDO CTSn RXD[0] TXD[0] TXD[1] TXD[2]
Ball
T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17
Signal
DSRn TMS gndr SFRM[1] INT[2] INT[0] USBp[1] NC NC NC NC P[8] P[4] P[1] DA[6] DA[3] AD[10] DA[0] TDO NC SCLK[1] SSPRX[1] INT[1] RTSn USBm[1] NC
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
The following section focuses on the EP9307 pin signals from two viewpoints - the pin usage and pad characteristics, and the pin multiplexing usage. The first table (Table S) is a summary of all the EP9307 pin signals. The second table (Table T) illustrates the pin signal multiplexing and configuration options. Table S is a summary of the EP9307 pin signals, which illustrates the pad type and pad pull type (if any). The symbols used in the table are defined as follows. (Note: A blank box means Not Applicable (NA) or, for Pull Type, No Pull (NP).) Under the Pad Type column: * A - Analog pad
* P - Power pad * G - Ground pad * I - Pin is an input only * I/O - Pin is input/output * 4mA - Pin is a 4mA output driver * 8mA - Pin is an 8mA output driver * 12mA - Pin is an 12mA output driver See the text description for additional information about bi-directional pins. Under the Pull Type Column: * * PU - Resistor is a pull up to the RVDD supply PD - Resistor is a pull down to the RGND supply
.
Table S. Pin Descriptions
Pin Name TCK TDI TDO TMS TRSTn BOOT[1:0] XTALI XTALO VDD_PLL GND_PLL RTCXTALI RTCXTALO WRn RDn WAITn AD[25:0] DA[31:0] CSn[3:0] CSn[7:6] DQMn[3:0] SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn P[17:0] SPCLK HSYNC Block JTAG JTAG JTAG JTAG JTAG System PLL PLL PLL PLL RTC RTC EBUS EBUS EBUS EBUS EBUS EBUS EBUS EBUS SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM Raster Raster Raster Pad Type I I 4ma I I I A A P G A A 4ma 4ma I 8ma 8ma 4ma 4ma 8ma 8ma 8ma 4ma 8ma 8ma 8ma 4ma 12ma 8ma Pull Type PD PD PD PD PD PU PU PU PU PU PU PU JTAG clock in JTAG data in JTAG data out JTAG test mode select JTAG reset Boot mode select in Main oscillator input Main oscillator output Main oscillator power, 1.8V Main oscillator ground RTC oscillator input RTC oscillator output SRAM Write strobe out SRAM Read/OE strobe out SRAM Wait in Shared Address bus out Shared Data bus in/out Chip select out Chip select out Shared data mask out SDRAM clock out SDRAM clock enable out SDRAM chip selects out SDRAM RAS out SDRAM CAS out SDRAM write enable out Pixel data bus out Pixel clock in/out Horizontal synchronization/ line pulse out Pin Name Description V_CSYNC BLANK BRIGHT PWMOUT Xp, Xm Yp, Ym sXp, sXm sYp, sYm VDD_ADC GND_ADC COL[7:0] ROW[7:0] USBp[2:0] USBm[2:0] TXD0 RXD0 CTSn DSRn DTRn RTSn TXD1 RXD1 TXD2 RXD2 MDC MDIO RXCLK MIIRXD[3:0] RXDVAL
Table S. Pin Descriptions (Continued)
Block Pad Type 8ma 8ma 4ma 8ma A A A A P G 8ma 8ma A A 4ma I I I 4ma 4ma 4ma I 4ma I 4ma 4ma I I I PU PD PD PD PU PU PU PU PU PU PU Pull Type PU PU Description Vertical or composite synchronization/frame pulse out Composite blanking signal out PWM brightness control out Pulse width modulator output Touchscreen ADC X axis Touchscreen ADC Y axis Touchscreen ADC X axis feedback Touchscreen ADC Y axis feedback Touchscreen ADC power, 3.3V Touchscreen ADC ground Key matrix column inputs Key matrix row outputs USB positive signals USB negative signals Transmit out Receive in Clear to send/transmit enable Data set ready/Data Carrier Detect Data Terminal Ready output Ready to send Transmit/IrDA output Receive/IrDA input Transmit Receive Management data clock Management data input/output Receive clock in Receive data in Receive data valid
Raster Raster Raster PWM ADC ADC ADC ADC ADC ADC Key Key USB USB UART1 UART1 UART1 UART1 UART1 UART1 UART2 UART2 UART3 UART3 EMAC EMAC EMAC EMAC EMAC
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Table S. Pin Descriptions (Continued)
Pin Name RXERR TXCLK MIITXD[3:0] TXEN TXERR CRS CLD GRLED RDLED EECLK EEDAT ABITCLK ASYNC ASDI ASDO ARSTn SCLK1 SFRM1 SSPRX1 SSPTX1 INT[2:0] PRSTn RSTOn EGPIO[15] EGPIO[13:0] FGPIO[7, 5, 0] GGPIO[2] HGPIO[7:2] vddc vddr gndc gndr Block EMAC EMAC EMAC EMAC EMAC EMAC EMAC LED LED EEPROM EEPROM AC97 AC97 AC97 AC97 AC97 SPI1 SPI1 SPI1 SPI1 INT Syscon Syscon GPIO GPIO GPIO GPIO GPIO Power Power Ground Ground Pad Type I 4ma I 4ma 4ma I I 12ma 12ma 4ma 4ma 8ma 8ma I 8ma 8ma 8ma 8ma I 8ma I I 4ma I/O, 4ma I/O, 4ma I/O, 8ma I/O, 8ma I/O, 8ma P P G G Pull Type PD PU PD PD PD PD PU PU PU PD PD PD PU PD PD PD PD PU PU PU PU PU PU Description Receive data error Transmit clock in Transmit data out Transmit enable Transmit error Carrier sense Collision detect Green LED Red LED EEPROM/Two-wire Interface clock EEPROM/Two-wire Interface data AC97 bit clock AC97 frame sync AC97 Primary input AC97 output AC97 reset SPI bit clock SPI Frame Clock SPI input SPI output External interrupts Power on reset User Reset in out - open drain Enhanced GPIO Enhanced GPIO GPIO GPIO GPIO Digital power, 1.8V Digital power, 3.3V Digital ground Digital ground
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Table T illustrates the pin signal multiplexing and configuration options.
Table T. Pin Multiplex Usage Information
Physical Pin Name
COL[7:0] ROW[7:0] EGPIO[0] EGPIO[1] EGPIO[2] EGPIO[3] EGPIO[4] EGPIO[5] EGPIO[6] EGPIO[7] EGPIO[8] EGPIO[9] EGPIO[10] EGPIO[11] EGPIO[12] EGPIO[13] EGPIO[15] ABITCLK ASYNC ASDO ASDI ARSTn SCLK1 SFRM1 SSPTX1 SSPRX1
Description
GPIO GPIO Ring Indicator Input 1Hz clock monitor DMA request HDLC Clock I2S Transmit Data 1 I2S Receive Data 1 I2S Transmit Data 2 DMA Request 0 DMA Acknowledge 0 DMA EOT 0 DMA Request 1 DMA Acknowledge 1 DMA EOT 1 I2S Receive Data 2 Device active / present I2S Serial clock I2S Frame Clock I2S Transmit Data 0 I2S Receive Data 0 I2S Master clock I2S Serial clock I2S Frame Clock I2S Transmit Data 0 I2S Receive Data 0
Multiplex signal name
GPIO Port D[7:0] GPIO Port C[7:0] RI CLK1HZ DMARQ HDLCCLK1 SDO1 SDI1 SDO2 DREQ0 DACK0 DEOT0 DREQ1 DACK1 DEOT1 SDI2 DASP SCLK LRCK SDO0 SDI0 MCLK SCLK LRCK SDO0 SDI0
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Copyright 2004 Cirrus Logic (All Rights Reserved)
DS667PP3
EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
Acronyms and Abbreviations
The following tables list abbreviations and acronyms used in this data sheet.
Term
ADC ALT AMBA ATAPI CODEC CRC DAC DMA
Term
OHCI PHY
Definition
Open Host Controller Interface Ethernet PHYsical layer interface Programmed I/O Reduced Instruction Set Computer Secure Digital Music Initiative Synchronous Dynamic RAM Serial Peripheral Interface Static Random Access Memory Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium Thin Film Transistor Translation Lookaside Buffer Universal Serial Bus
Definition
PIO Analog-to-Digital Converter RISC Alternative SDMI Advanced Micro-controller Bus Architecture SDRAM ATA Packet Interface SPI COder/DECoder SRAM Cyclic Redundancy Check Digital-to-Analog Converter Direct-Memory Access TFT STA
EEPROM Electronically Erasable Programmable Read Only Memory TLB EMAC EBUS FIFO FIQ FLASH GPIO HDLC I/F I 2S IC ICE IDE IEEE IrDA IRQ ISO JTAG LFSR MII MMU Ethernet Media Access Controller USB External Bus First In/First Out Fast Interrupt Request Flash memory General Purpose I/O High-level Data Link Control Interface Inter-IC Sound Integrated Circuit In-Circuit Emulator Integrated Drive Electronics Institute of Electronics and Electrical Engineers Infrared Data Association Standard Interrupt Request International Standards Organization Joint Test Action Group Linear Feedback Shift Register Media Independent Interface Memory Management Unit
Units of Measurement
Symbol Unit of Measure
degree Celsius Hertz = cycle per second Kilobits per second Kilobyte KiloHertz = 1000 Hz Megabits per second MegaHertz = 1,000 KiloHertz microAmpere = 10-6 Ampere microsecond = 1,000 nanoseconds = 10-6 seconds milliAmpere = 10-3 Ampere millisecond = 1,000 microseconds = 10-3 seconds milliWatt = 10-3 Watts nanosecond = 10-9 seconds picoFarad = 10-12 Farads Volt Watt
C
Hz Kbps Kbyte KHz Mbps MHz A s mA ms mW ns pF V W
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EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen
ORDERING INFORMATION
The order numbers for the device are: EP9307-CR EP9307-CRZ EP9307-IR EP9307-IRZ 0C to +70C 0C to +70C -40C to +85C -40C to +85C 272 pin TFBGA 272 pin TFBGA 272 pin TFBGA 272 pin TFBGA
Lead Free Lead Free
EP9307 -- CRZ
Lead Material: Z = Lead Free Part Number Product Line: Embedded Processor Package Type: R = 272 pin TFBGA Temperature Range: C = Commercial E = Extended Operating Version I = Industrial Operating Version
Note:
Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation. Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola is a registered trademark of Motorola, Inc. LINUX is a registered trademark of Linus Torvalds.
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